Thermo-Mechanical Stress in Cu TSV Arrays
Heterogeneous Integration course, SSIs M.Sc. · Autumn 2024 · Academic project · Individual
3D COMSOL study of thermal-expansion mismatch stress in copper through-silicon-via arrays over a 25 to 400 C cycle, comparing an SiO2 liner against a compliant polymer liner.
- COMSOL
- TSV
- 3D integration
- Stress analysis
- Packaging
Overview
Through-silicon vias make 3D integration possible, but copper expands about six times faster than silicon when heated. This study quantifies what that mismatch does to stress around a via array during a thermal cycle, and whether a compliant liner helps.
Technical approach
- 3D COMSOL model of a four-via Cu TSV array (about 30 um vias) in a silicon domain with an SiO2 liner
- Thermal cycle from 25 C up to 400 C and back, with copper plasticity included
- Repeat with a compliant polymer-like liner (3 GPa modulus, higher CTE) for comparison
- Compared von Mises stress, displacement, and plastic strain fields
Results
- Peak von Mises stress of about 700 MPa concentrated near the copper via boundaries at 400 C, well above the copper yield strength used (250 MPa), with residual stress around 150 MPa after cool-down
- The compliant liner dropped peak via stress to about 100 MPa with no plastic strain, at the cost of process complexity
- Results connect directly to keep-out-zone rules for active devices near TSVs in 3D ICs
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