Embedded Systems & FPGA

My embedded work spans synthesizable VHDL on Altera FPGAs with full simulation and timing analysis, automated hardware-in-the-loop testing with LabVIEW and NI DAQ hardware, and Raspberry Pi based sensor nodes. Most of it comes from the Smart Systems master's, on top of an electrical and computer engineering degree.

Embedded & FPGA Engineer CV (PDF)(2026-09)

Projects

Simulated waveform of an elk sound with threshold lines and seven-segment displays showing Lo, Err, and High

FPGA Frequency Measurement and Acoustic Event Classification

System-Level Design, SSIs M.Sc. (USN/BME) · Autumn 2025

A hierarchical VHDL system that measures an input signal's frequency and classifies acoustic events into bands, verified in ModelSim and synthesized on an Altera Cyclone III with full timing closure.

VHDL
FPGA
ModelSim
Quartus

Black enclosure with a small solar panel mounted on top

Animal Watch: Wildlife Acoustic Monitoring Node

Aalto University (Technology Entrepreneurship) · 2024

A solar-powered Raspberry Pi sensor node prototype for reducing elk-vehicle collisions: microphone arrays for direction-of-arrival estimation, an ML sound classifier, and environmental sensing, developed as a technology entrepreneurship project at Aalto.

Raspberry Pi
Audio ML
YAMNet
Sensor node

LabVIEW test sequence results with pass/fail indicator lights

Automated Hardware-in-the-Loop Validation of a DC-DC Converter

Virtual Instrumentation course, SSIs M.Sc. (BME) · Dec 2025

A LabVIEW test system that switches loads programmatically and validates an LM2596 buck converter against pass/fail criteria using NI USB-6001 DAQ hardware.

LabVIEW
NI DAQ
HIL testing
Power electronics

ModelSim waveform of the password verification FSM states

Synchronous VHDL Building Blocks and Password FSM

System-Level Design, SSIs M.Sc. · 2025

A set of synchronous digital modules in VHDL, each with its own ModelSim testbench: counters, shift registers, dividers, BCD display drivers, and a nine-state password-verification FSM with a generic-configurable output hold time.

VHDL
ModelSim
FSM
RTL design

LabVIEW Coursework: Patterns and Test Frameworks

Virtual Instrumentation course, SSIs M.Sc. · 2025

LabVIEW labs covering functional-global timers, notifier and queue based producer-consumer animation, and a pressure-warning system tested with editable test vectors.

LabVIEW
Producer-consumer
Test vectors

Skills

FPGA & digital design: VHDL, synchronous RTL design, FSMs, parameterized (generic) design, testbench development, ModelSim, Quartus, TimeQuest static timing analysis; Evidence: Frequency-measurement system synthesized for an Altera Cyclone III with full timing closure.
Test & measurement: LabVIEW, NI DAQ (USB-6001), hardware-in-the-loop test automation, test-vector design; Evidence: Automated pass/fail validation of a DC-DC converter.
Embedded platforms: Raspberry Pi, Arduino, sensor integration, UDP/TCP device protocols; Evidence: Animal Watch wildlife monitoring node; thesis camera-node forwarders.