Synchronous VHDL Building Blocks and Password FSM

System-Level Design, SSIs M.Sc. · 2025 · Academic project · Individual

A set of synchronous digital modules in VHDL, each with its own ModelSim testbench: counters, shift registers, dividers, BCD display drivers, and a nine-state password-verification FSM with a generic-configurable output hold time.

VHDL
ModelSim
FSM
RTL design
Testbenches

Overview

Coursework that builds the vocabulary of synchronous design one module at a time, with waveform-verified behaviour for each: shift registers implemented in two different styles, event counters, a frequency divider, BCD counters with seven-segment decoding, a coin-accumulator Moore FSM, and a password-sequence FSM.

Technical approach

Nine-state password FSM with enumerated state types, validating a multi-digit input sequence and driving accept/reject outputs
A refactored generic version where the output hold time is a VHDL generic, separating state-transition logic from output timing
Shift register implemented both with numeric_std shift operations and with explicit cascaded flip-flops
A dedicated testbench per module with clock and stimulus generation, managed as one ModelSim project

Media

ModelSim waveform of the password verification FSM states — ModelSim verification of the password FSM: state trace through correct_one to correct_all, then wrong-sequence paths driving the reject output.

ModelSim waveform of the coin accumulator FSM — Value-accumulator FSM testbench: enumerated states stepping zero through final under different input sequences.